1. Field of Invention
This invention is concerned with a circuit for recovering a clock signal from an input data stream signal and, more particularly, with such a circuit using a dual servo or, more particularly, a dual phase lock loop to more quickly lock onto the frequency of the input data stream signal.
2. Description of the Prior Art
In systems involving the transmission of digital data including an embedded clock signal, digital communication links and networks utilize various schemes for receiver clock recovery from the encoded digital data stream. A particular technique is selected and optimized to fulfill system requirements. Phase lock loops (digital, analog, and hybrid) in various configurations, high Q bandpass filter techniques and various digital edge referenced retiming schemes are typical candidates. Constraints such as system configuration, operating mode (burst or continuous), data rate, channel bandwidth, message overhead, transceiver coupling, etc., must be taken into account when selecting a clock recovery technique.
An exemplary (but not limiting) example of a burst mode communication system is shown in FIG. 1, to be discussed in more detail hereinafter. This is a fiber optic based, star coupled local area network (FOLAN) configuration. The outputs of all fiber optic transmitters are mixed in the star coupler and sent to each fiber optic receiver. This forms an "optical bus". The bus interface unit (BIU) performs the "connectivity function" from each user(s) at a location to the local area network. This particular configuration provides versatile and efficient user interconnect environment.
In FIG. 2, also to be discussed in detail hereinafter, the internal functional details of the BIU are shown. Bus transmission and reception circuits are delineated in particular. The modulator circuit takes the user data stream and digitally encodes it in preparation for transmission. This circuit typically uses a stable, accurate frequency source, such as a crystal oscillator, for baseband modulation. One (of several) reason this encoding is performed is to "embed" clocking information in the transmitted data stream for use at each BIU receiver.
The receive portion of a BIU performs clock recovery (or extraction) from the incoming data stream and sends this clocking information to the demodulator circuit in order to decode the data. This stream is sent to the remaining BIU circuits and eventually to the appropriate user(s).
One of the ma]or problems associated with the above-described FOLAN system is the necessity to "gate" or burst the outgoing messages from each BIU to prevent message collisions at the receivers. Circuits for recovering clock, therefore, must respond to, or stabilize rapidly upon receipt of, the message burst in order to maintain an efficient system.
The decision to use a particular clock recovery scheme is based upon many factors, but one of the major ones is the choice of allowable data encoding schemes. The transmission medium bandwidth is a premium resource (especially in &gt;100 megabit/second systems) and thus an encoding scheme that has the best (highest) unencoded bandwidth/encoded bandwidth (efficiency) ratio (to a maximum of 1.0) is desired. A phase-lock clock recovery method is typically superior to other methods when it is desired or necessary to maintain a ratio of approximately .gtoreq.0.7.
Locking a local receiver oscillator to the incoming data stream is a typical way of recovering clock in communication systems, to be discussed in detail hereinafter. FIG. 3 shows a typical prior art receiver using a phase lock loop (PLL) scheme for clock recovery. Incoming data is modified (typically by a signal differention block, d/dt as shown) to enhance the spectral output at the clock frequency, and sent to the phase lock loop circuit which locks to the received bit stream. Such a phase lock loop circuit outputs both the data reclocked with the clock information and the recovered clock signal.
Although many various schemes for phase lock loop circuits have been designed for clock recovery (similar to the one just described), designing burst-mode responsive PLL's is considerably more difficult. Minimization of the locking or acquisition process can be accomplished with such PLL circuit enhancements as loop bandwidth widening, voltage controlled oscillator (VCO) frequency sweeping, etc. In all of these design enhancements, frequency and phase acquisition occur consecutively. Frequency acquisition is typically more difficult and takes longer. Thus, all of these schemes (in general) seek to reduce the frequency acquisition portion of the lock process, and once this is achieved, phase acquisition will (or should) occur rapidly.
In the loop bandwidth widening method, acquisition is sped up by "opening up" the loop bandwidth with a circuit that detects a loss of lock (or out of lock) condition. Wider initial loop bandwidth enhances the frequency acquisition ability of the PLL and once lock is detected, the bandwidth is restricted to enhance noise performance, etc. Typical circuits electrically switch in and out components in the loop filter feedback network. This technique requires at least two auxiliary circuits (the lock detect and the loop switch logic) and is thus rather cumbersome. The high frequency degradation and transient noise induction due to the switch circuitry in the loop filter is also of considerable concern.
The frequency sweep method uses an auxiliary circuit to sweep the VCO center frequency (unlocked) in search of the input's clock frequency. The circuit stops sweeping when lock detect occurs. Since the input frequency relative to the sweeping VCO frequency, at the instant of input burst reception, is unknown and thus a random process, improvement in frequency acquisition time is only an average over all time. Also, the rate of sweep has an upper bound, limited by the response time of the loop elements. The overall phase lock loop circuit using this technique has similar complexity problems of the previous method, i.e., the loop bandwidth widening method.
A phase lock loop circuit utilized in a token ring network which utilizes a local oscillator to enhance frequency acquisition is disclosed in an article entitled "Architecture and Design of a Reliable Token Ring Network," by Werner Bux et al., appearing in the IEEE Journal on Selected Areas in Communications, November 1983, pp. 756-765. That article, as illustrated in FIG. 5, shows that either the data in (including an embedded clock signal) or a crystal oscillator local to the receiving circuit is utilized via multiplexer (MUX) to control a single loop filter. The disadvantages of this circuit relative to the phase lock loop circuit of the instant invention, which uses a pair of filters, will be discussed hereinafter.